1. Field of the Invention
This invention is related to programmable logic circuits, and more specifically, to a programmable logic circuit architecture using resistive memory elements.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” (Each of these publications is incorporated by reference herein.)
A Field Programmable Gate Array (FPGA) is a representative programmable logic circuit. FIG. 1 shows the state-of-art island-based FPGA architecture with segmented channels, wherein an FPGA 100 is comprised of an array of tiles 102, and each tile 102 consists of one logic block (LB) 104, two connection blocks (CB) 106, and one switch block (SB) 108. Each LB 104 contains a cluster of basic logic elements, typically look-up tables (LUTs), to provide customizable logic functions. The LBs 104 are connected to segmented routing channels 110 through the CBs 106, and the segmented routing channels 110 are connected with each other through SBs 108.
Callout blocks 112 and 114 depict two typical circuit designs for CBs 106 and SBs 108, respectively, based on multiplexers (MUXs) 116 and buffers 118. The selector pins of each multiplexer 116 are connected to a group of static random access memory (SRAM) cells 120 that control and program its connectivity. The circuits in FIG. 1 have copies of up to the number of pins per side of LBs 104 in a single CB 106, and up to the number of tracks per channel in a single SB 108.
In existing FPGAs, CBs and SBs make up the interconnects of FPGAs with much larger area and higher complexity as compared to the direct interconnects of an Application Specific Integrate Circuit (ASIC). Actually, the programmable interconnects are the dominant part of an FPGA. As shown in the two circuit designs 112, 114 in FIG. 1, the circuit components of programmable interconnects include MUX-based routing switches 116, routing buffers 118, and SRAM cells 120. All of them are non-trivial, but have fundamental weak points.
The MUX-based routing switches 116 have high serial resistance and need large transistor width (and hence large area) to overcome it. The routing buffers 118 are extensively fabricated and used due to their fixed locations in programmable interconnects which cannot be optimized according to design demand. The storage overhead of SRAM cells 120 is as high as six transistors per bit.
Some literature [1] proposes to improve FPGA architecture using non-volatile memory elements. Consider, for example, FIGS. 7 and 18 of [1], wherein the SRAM-based pass transistors in MUXs in FPGAs as shown in FIG. 7 of [1] are replaced with non-volatile resistive memory elements as shown in FIG. 18 of [1]. However, this direct replacement leads to high overhead of programming circuits for resistive memory elements, which undermines the benefit brought by the replacement. Also, the method in [1] does not solve the problem of extensive fabrication of routing buffers.
Other literature [2] proposes to provide programmable interconnects using nanowire crossbars, as shown in FIG. 2 of [2]. FIGS. 2A and 2B illustrate cells 200 with output and/or input pads 202 of logic gates 204 that may be interconnected using nanowire crossbars 206. This prior art also replaces LUTs in FPGA with simple logic gates. The connections between nanowires are determined by reconfigurable junctions between two nanowire layers. The method in [2] leads to speed degradation and high power consumption due to large capacitance of nanowires.
Nonetheless, what is needed is a redesign of programmable interconnects of FPGA in light of the technology development of resistive memory elements. The present invention satisfies this need.